1. Field of the Invention
This invention generally relates to generating frequency signals, and more particularly to a system and method for controlling the frequency range of a delay-locked loop circuit.
2. Description of the Related Art
Delay-Locked Loop(DLL) circuits are desirable because of their ability to produce a stable output frequency synchronized with the period of an input reference signal. These circuits are most commonly used to generate clock signals for controlling the speed and operation of microprocessor systems and timing signals for transferring data in various data storage applications.
FIG. 1 shows a conventional delay-locked loop circuit which includes a phase detector 1, a control generator 2, and a programmable delay circuit 3, which is initially set to some arbitrary delay and thereafter is controlled by the control generator. In operation, the phase detector outputs a signal corresponding to a difference in phase between an input clock signal CKin and an output clock signal CKdly. The difference signal is input into the control generator and the generator responds by outputting a control signal to the delay circuit. The delay circuit then delays the input clock signal by an amount which reduces the phase difference between the input and output clock signals. Because the phase detector continuously compares the input and output clock signal phases, the output of the delay-locked loop is assured of being locked onto the period of the input clock signal.
Structurally, the phase detector includes a circuit which generates Up or Down signals for increasing or decreasing the delay based on a polarity of the phase difference between the clock signals. The control generator includes an integrator for integrating the phase-difference, a loop filter for filtering the output of the integrator to provide stabilizing control, and a signal-generation circuit for generating a control signal for setting the amount of delay in the delay circuit. Finally, the delay circuit includes a chain of delay elements which delay the input clock signal by an amount which corresponds to the voltage of the control signal output from the control generator.
While conventional delay-locked loop circuits have proven reliable for purposes of generating an output frequency signal having stable synchronized period, they are not without drawbacks. One significant drawback relates to their inability to accurately determine the extent of delay between the input and output clock signals in terms of numbers of clock periods. Put differently, the phase detector in conventional DLL circuits cannot determine, for example, whether a detected phase difference resulted from the input and output clock signals being 90 degrees out-of-phase or 450 degrees out of phase. This situation is depicted in FIG. 2, where the difference between the leading edges of the input and output clock signals measures one clock period (360xc2x0) plus 90 degrees.
When this situation occurs, the delay unit maybe controlled by the control generator to place the input and output clock signals in phase with one another, but in so doing the output clock signal may differ from the input clock signal by one or more clock periods. This situation is depicted in FIG. 3, where the output clock signal CKdly is separated an integer number K clock periods from the input clock signal. Here, it is clear that the output clock signal CKdly is indistinguishable in appearance whether it is separated from the input clock signal by one clock period or multiple clock periods. As a result, conventional DLL circuits are susceptible to operating outside their effective operating frequency ranges, which results in a substantial degradation in performance. For example, the input clock signal maybe delayed by an improper amount and as a result significant phase error may persist between the input and output clock signals. This situation may be more clearly understood as follows.
Because the phase detector in a conventional DLL circuit cannot determine whether the delay between the input clock signal and output clock signal spans across multiple clock periods, its operating frequency range must necessarily be limited in order to prevent this condition from occurring. (This condition maybe referred to as an out-of-bounds condition.) Put differently, to prevent the DLL circuit from locking on to multiple clock periods, the circuit must be designed to operate in a narrow frequency range. As a result, use of conventional DLL circuits must be limited to only those applications which operate within the DLL operational frequency range.